The 65020

This page is incomplete. Beware.

The 65020 is an attempt to extend the 6502 to a more modern 32 bit design. This page might be a little difficult to understand if you are not familiar with the 6502.

The basic trick involved is to extend the 6502's concept of a byte to a 16 bit word. Opcodes take one byte, so they are now 16 bits. Addresses take two bytes, so they are now 32 bits. The instruction set is designed so that it behaves like the old 8 bit processor if the top 8 bits of each word are set to '1'.

Memory

Memory consists of 4G of 16 bit words. The unit of addressing is the 16 bit word, but it cannot be manipulated directly. The only data types supported by the processor are the 8 bit byte (in the bottom 8 bits of a memory location or a register), and the 32 bit longword (in two consecutive memory locations or in a register). Longwords may be stored at any word address - there may be a speed advantage in keeping them 32 bit aligned, but the processor does not require this.

Addresses

Addresses are now 32 bits, but they are stored in a rather unusual way. If two consecutive locations contain $aabb and $ccdd, they location they point to is $ccaaddbb. This keeps old 8 bit code in the top 64K of memory.

32 bit data is stored in the same format.

Registers

There are four of each of the A, X, and Y registers. They are all 32 bits wide. There is a fourth group of registers containing PC, SP, Z0, and Z1. It is strongly recommended that Z0 be set to 0.

Instructions

The 6502 had 256 potential opcodes, but it didn't use all of them. If the gaps are filled, it is possible to give almost all memory-using instructions a full set of the useful addressing modes - ABS,X, ABS,Y, (ABS,X), (ABS),Y, and ACC. Zero page is considered 'not useful'.

The 65020 instruction set in a rather ugly example of an HTML table. HTML is not my best language.

The only instruction added to the original set is PSH - push immediate. It takes the slot you'd expect STA immediate to have. All other new operations are implemented through the 'P' bit (see below).

Instruction Groups

For convenience, I've divided instructions into 11 groups:
0:ADC AND CMP EOR LDA ORA SBC STA
1:ASL DEC INC LSR ROL ROR
2:BCC BCS BEQ BMI DNE BPL BVC BVS
3:BIT JMP JSR
4:BRK
5:CLC CLD CLI CLV SEC SED SEI NOP
6:CPX CPY LDX LDY STX STY
7:DEX DEY INX INY
8:PHA PHP PLA PLP PSH
9:RTI RTS
10:TAX TAY TSX TXA TXS TYA

Instruction Formats

There are four formats for the top half (the extension) of the opcodes:
0:PDRRSSSSused by ACC modes, PHA, RTS, TAX groups
1:PDNNNXXXused by DEX group
2:PVVVVVVVused by BRK group
3:PDRRIXXXused by all others
P: Operation Select. '1' means use the standard operation (the 6502 instruction). '0' means use the alternate operation. The alternate to ADC is ADD (add without carry). The alternate to the branch instructions are branch instructions with the rest of the useful conditions (including always).

D: Data Size. '1' means this is an 8 bit instruction. '0' means it is a 32 bit instruction.

R: Main Register Select. On an LDA instruction, for example, it selects one of the four A registers. On CPX, it selects one of four X registers.

I: Index Size. '1' means the index (if it is used) is 8 bits (the bottom 8 bits of the register). '0' means the index is 32 bits.

X: Index Register Select.
000:PC100:X0/Y0
001:Z0101:X1/Y1
010:Z1110:X2/Y2
011:SP111:X3/Y3
Now any instruction with an indexed addressing mode can use PC or SP as the index. This makes relocatable code and accessing parameters on the stack very easy.

N: Constant to INC/DEC by.
000:8100:4
001:7101:3
010:6110:2
011:5111:1
This field is only used by the DEX group, and not by INC or DEC. Since the DEX group uses XXX to select the register, it is able to increase or decrease the stack pointer by small amounts.

S: Stack Register Select / Second Register Select.
0000:A01000:X0
0001:A11001:X1
0010:A21010:X2
0011:A31011:X3
0100:Y01100:PC
0101:Y11101:Z0
0110:Y21110:Z1
0111:Y31111:SP
The ACC modes and the TAX group have to shuffle the registers around to get the correct default as 1111. This simply means inverting one or both of the top two bits.

The ACC mode uses this field to select the second register. All of the ADC group instructions now have an ACC mode, and the ACC mode can access any register. Register-to-register operations are now possible, as long as the destination is an A register.

V: BRK vector number. The vector is at $FFFFFF00+2*V.

Comments

BRK, JSR, and hardware interrupts always push all 32 bits of PC. RTI and RTS always pop all 32 bits.

ASL group instructions with ACC mode use the S field to select the register instead of the R field. This means they can work on any register.

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